In the simplest implementation, conventional magnetic random access memory (MRAM) cells comprise at least a magnetic tunnel junction formed of two magnetic layers separated by a thin insulating layer, where one of the layer, the so-called reference layer, is characterized by a fixed magnetization and the second layer, the so-called storage layer, is characterized by a magnetization which direction can be changed upon writing of the memory. When the respective magnetizations of the reference layers and the storage layer are antiparallel, the resistance of the magnetic tunnel junction is high (Rmax), corresponding to a low logic state “0”. On the other hand, when the respective magnetizations are parallel, the resistance of the magnetic tunnel junction becomes low (Rmin), corresponding to a high logic state “1”.
The logic state of the MRAM cell is usually read by comparing its resistance state to a reference resistance Rref, preferably derived from a reference cell or an array of reference cells, with a reference resistance of typically Rref=(Rmin+Rmax)/2, combined in-between the magnetic tunnel junction resistance of the high logic state “1” and the resistance of the low logic state “0”. Here, the respective resistance states of the MRAM cell and reference resistance Rref is typically measured simultaneously by passing two distinct sense currents within the MRAM cell and the reference cell or an array of reference cells. The two sense currents are then compared in order to determine the logic state of the MRAM cell.
US Patent Application No. 2006/0158945 discloses a readout circuit for a self-referenced memory cell array comprising several of MRAM cell. The readout operation on a selected MRAM cell comprises subsequently performing a first write with a first low (or high) resistance storage state, performing a first readout by measuring a first current, performing a second write with a second high (or low) resistance storage state, and performing a second readout by measuring a second current. The readout circuit comprises a preamplifier for converting the first current to an output voltage, voltage storage means for holding the output voltage, and voltage comparator means for comparing the output voltage from an output voltage from the comparator (second current). The above readout circuit requires performing sequentially the first write and readout and second write and readout, and is therefore time consuming. Compared to conventional MRAM cells, the self-referenced MRAM cell with two-cycle read operation requires a sensibly more complex reading circuit with controlled timing signals for the two read cycles.
In unpublished European patent application, No. 09290563, filed on Jul. 13, 2009 by the present applicant, a self-referenced MRAM cell is described, comprising a method of reading the logic state of the MRAM cell. The method comprises a write operation, where data is written into storage layer of the magnetic tunnel junction by switching the storage layer magnetization, and a two-cycle read operation. More particularly, during the first cycle of the read operation, the magnetization of the sense layer is aligned with a first read magnetic field and the corresponding first resistance value of the magnetic tunnel junction is stored. During the second cycle of the read operation, the magnetization of the sense layer is aligned with a second read magnetic field and the corresponding second resistance value of the magnetic tunnel junction is compared with the stored value of the first resistance value measured during the first read cycle. The logic state of the MRAM cell is determined from the sign, positive or negative, of the difference in the first and second resistance values.
FIG. 1 shows a schematic representation a conventional readout circuit 100 for performing the two-cycle read operation of the self-referenced MRAM cell described in European patent application No. 09290563. The conventional readout circuit 100 comprises a reading circuit 20 including a source transistor (not shown) capable of sourcing a sense current for measuring the first and second resistance value of the magnetic tunnel junction. The conventional readout circuit 100 also comprises a sample and hold circuit 21 using a capacitance (not shown) to store the first resistance value, and a comparator 22 for determining the logic state of the MRAM cell. The logic state can be amplified to a rail-to-rail signal.
The controllable readout circuit 100 does not allow for controlling the first and second readout timing after completion of the MRAM cell and readout circuit fabrication.